A CPU Instruction Set Details



Format:

ADDI rt, rs, immediate

Description:

The 16-bit immediate is sign-extended and added to the contents of general register rs to form the result. The result is placed into general register rt. In 64-bit mode, the operand must be valid sign-extended, 32-bit values.

An overflow exception occurs if carries out of bits 30 and 31 differ (2's complement overflow). The destination register rt is not modified when an integer overflow exception occurs.

Operation:

Exceptions:

Integer overflow exception

Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96

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