16.2 R4400 Master/Checker Mode
Cross-Coupled Checking Configuration
In the Cross-Coupled Checking configuration, one of the R4400 processors drives the data bus pins and is labelled the System Interface Master (mode bits 42 and 18 = 102). The other R4400 processor drives the ECC or parity check pins on the same bus and is labelled the Secondary Cache Master (mode bits 42 and 18 = 012). This is shown in Figure 16-6.
Both processors monitor the buses and indicate a miscomparison by asserting their respective Fault* signals. The Fault* signal indicates error conditions not specifically covered by R4400 processor exceptions.*1
Figure 16-6 Cross-Coupled Configuration of Master/Checker Mode
The signals that are connected in parallel and driven from the System Interface Master (1 in Figure 16-6) include:
- SysAD(63:0)
- SysCmd(8:0)
- SCAPar(2:0)
Signals that are connected in parallel and driven from the Secondary Cache Master (2 in Figure 16-6) include:
- SysADC(7:0)
- SysCmdP
- ValidOut*
- Release*
- SCAddr(17:1)
- SCAddr0(W:Z)
- SCOE*
- SCWr(W:Z)*
- SCData(127:0)
- SCDChk(15:0)
- SCTag(24:0)
- SCTChk(6:0)
- SCDCS*
- SCTCS*
It should be noted that the fault detection mechanism associated with the Fault* pin does not cause any exceptions; the processor continues to run normally regardless of the state of the Fault* signal. It is up to external logic to handle an asserted Fault* signal.
Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96
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