2. CPU Instruction Set Summary
2.1 CPU Instruction Formats
Each CPU instruction consists of a single 32-bit word, aligned on a word boundary. There are three instruction formats--immediate (I-type), jump (J-type), and register (R-type)--as shown in Figure 2-1. The use of a small number of instruction formats simplifies instruction decoding, allowing the compiler to synthesize more complicated (and less frequently used) operations and addressing modes from these three formats as needed.
Figure 2-1 CPU Instruction Formats
In the MIPS architecture, coprocessor instructions are implementation-dependent; see Appendix A for details of individual Coprocessor 0 instructions.
Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96
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