16.2 R4400 Master/Checker Mode
Connecting a System in Lock Step
By operating in lock step, a system with more than one R4400 processor can be configured to improve data integrity. In such a configuration, output signals and I/O buses used during output are connected in parallel between the processors. One processor is defined at boot time as a bus driver, and the remaining processor(s) is defined as a bus monitor. Starting with the assertion of Reset*, all microprocessors must be synchronous, and execute identical operations on a cycle-by-cycle basis. The processor(s) designated as bus monitor compares the outputs and buses at bus-cycle boundaries, and asserts the Fault**1 signal on any mismatch.
In a lock step operation, the following R4400 signal groups are connected in parallel:
- System interface
- Secondary Cache interface (R4400SC and R4400MC only)
- Interrupt interface
The following signals are not connected in parallel:
- Initialization interface, ModeClock, ModeIn, and Reset* signals
- JTAG interface signals, JTDO and JTMS
- all Clock/Control interface signals except VssP and VccP
The remaining processor signals can be connected either in parallel or independently.
Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96
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