16.1 Error Checking in the Processor

Error Checking Operation

The processor verifies data correctness by using either the parity or the SECDED code as it passes data from the System interface to the secondary cache, or it moves data from the secondary cache to the primary caches or to the System interface.

System Interface

The processor generates correct check bits for doubleword, word, or partial-word data transmitted to the System interface. As it checks for data correctness, the processor passes data check bits from the secondary cache, directly without changing the bits, to the System interface if the interface is set to ECC mode. If the System interface is set to parity mode, the processor indicates a secondary cache ECC error by corrupting the state of the SysCmdP signal.

The processor does not check data received from the System interface for external updates and external writes. By setting the SysCmd(4) bit in the data identifier, it is possible to prevent the processor from checking read response data from the System interface.

The processor does not check addresses received from the System interface, but does generate correct check bits for addresses transmitted to the System interface.

The processor does not contain a data corrector; instead, the processor takes a cache error exception when it detects an error based on data check bits. Software, in conjunction with an off-processor data corrector, is responsible for correcting the data when SECDED code is employed.

Secondary Cache Data Bus

The 16 check bits, SCDChk(15:0), for the 128-bit secondary cache data bus are organized as 8 check bits for the upper 64 bits of data, and 8 check bits for the lower 64 bits of data.

System Interface and Secondary Cache Data Bus

The 8 check bits, SysADC(7:0), for the System interface address and data bus provide even-byte parity, or are generated in accordance with a SECDED code that also detects any 3- or 4-bit error in a nibble. The 8 check bits for each half of the secondary cache data bus are always generated in accordance with the SECDED code.

Secondary Cache Tag Bus

The 7 check bits, SCTChk(6:0), for the secondary cache tag bus are generated in accordance with the SECDED code, which also detects any 3- or 4-bit error in a nibble.

The processor generates check bits for the tag when it is written into the secondary cache and checks the tag whenever the secondary cache is accessed.

The processor contains a corrector for the secondary cache tag; the tag corrector is not in-line for processor accesses due to primary cache misses. The processor traps when a tag error is detected on a processor access due to a primary cache miss. Software, using the processor cache management primitives, is responsible for correcting the tag. When executing the cache management primitives, the processor uses the corrected tag to generate write back addresses and cache state.

For external accesses, the tag corrector is in-line; that is, the response to external accesses is based on the corrected tag. The processor still traps on tag errors detected during external accesses to allow software to repair the contents of the cache if possible.

System Interface Command Bus

In the R4000 processor, the System interface command bus has a single parity bit, SysCmdP, that provides even parity over the 9 bits of this bus. The SysCmdP parity bit is generated when the System interface is in master state, but it is not checked when the System interface is in slave state. In the R4400 processor, input parity is reported through the Fault* pin.

When the System interface is set to parity mode, the processor indicates a secondary cache ECC error by corrupting the state of the SysCmdP signal.

Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96

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