Parity is the simplest error detection scheme. By appending a bit to the end of an item of data--called a parity bit--single bit errors can be detected; however, these errors cannot be corrected.
There are two types of parity:
- Odd Parity adds 1 to any even number of 1s in the data, making the total number of 1s odd (including the parity bit).
- Even Parity adds 1 to any odd number of 1s in the data, making the total number of 1s even (including the parity bit).
Odd and even parity are shown in the example below:
The example above shows a single bit in Data(3:0) with a value of 1; this bit is Data(1).
- In even parity, the parity bit is set to 1. This makes 2 (an even number) the total number of bits with a value of 1.
- Odd parity makes the parity bit a 0 to keep the total number of 1-value bits an odd number--in the case shown above, the single bit Data(1).
The example below shows odd and even parity bits for various data values:
Parity allows single-bit error detection, but it does not indicate which bit is in error--for example, suppose an odd-parity value of 00011 arrives. The last bit is the parity bit, and since odd parity demands an odd number (1,3,5) of 1s, this data is in error: it has an even number of 1s. However it is impossible to tell which bit is in error. To resolve this problem, SECDED ECC was developed.
SECDED ECC Code
The ECC code chosen for processor secondary cache data and tag is single-bit error correction and double-bit error detection (SECDED) code.*1 SECDED ECC code is an improvement upon the parity scheme; not only does it detect single- and certain multi-bit errors, it corrects single-bit errors.
Secondary Cache Data Bus SECDED Code
The SECDED code protecting secondary cache data bus has the properties listed below:
- It corrects single-bit errors.
- It detects double-bit errors.
- It detects 3- or 4-bit errors within a nibble.
- It*2 provides 64 data bits protected by 8 check bits, and yields 8-bit syndromes (the syndrome is a generated value used to detect an error, and locate the position of the single bit in error).
- It is a minimal-length code; each parity tree used to generate the 8-bit syndrome has only 27 inputs, the minimum number possible.
- It provides byte Exclusive-ORs (XORs) of the data bits as part of the XOR trees used to build the parity generators. This allows selection of byte parity out of the XOR trees that generate or check the code.
- Single-bit errors*3 are indicated either by syndromes that contain exactly three 1s, or by syndromes that contain exactly five 1s (in which bits 0-3 or bits 4-7 of the syndrome are all 1s).
- Double-bit errors are indicated by syndromes that contain an even number of 1s.
- 3-bit errors within a nibble are indicated by syndromes that contain five 1s, in which bits 0-3 of the syndrome and bits 4-7 of the syndrome are not all 1s.
- 4-bit errors within a nibble are indicated by syndromes that contain four 1s. Because this is an even number of 1s, 4-bit errors within a nibble look like double-bit errors.
Secondary Cache Tag Bus SECDED Code
The SECDED ECC code protecting the secondary cache tag bus has the following properties:
- It corrects single-bit errors.
- It detects double-bit errors.
- It detects 3- or 4-bit errors within a nibble.
- It provides 25 data bits protected by 7 check bits, yielding 7-bit syndromes.
- It provides byte XORs of the data bits as part of the XOR trees used to build the parity generators. This allows selection of byte parity out of the XOR trees that generate or check the code.
- Single-bit errors are indicated by syndromes that contain exactly three 1s. This makes it possible to decode the syndrome to find which data bit is in error with 3-input NAND gates. For the check bits, a full 7-bit decode of the syndrome is required.
- Double-bit errors are indicated by syndromes that contain an even number of 1s.
- 3-bit errors within a nibble are indicated by syndromes that contain either five 1s or seven 1s.
- 4-bit errors within a nibble are indicated by syndromes that contain either four 1s or six 1s. Because these are even numbers of 1s, 4-bit errors within a nibble look like double-bit errors.
Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96
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