14. JTAG Interface
14.4 Implementation-Specific Details
This section describes details of JTAG boundary-scan operation that are specific to the processor.
- The MasterClock, MasterOut, SyncIn, and SyncOut signal pads do not support JTAG.
- The following pairs of output pads share a single JTAG bit:
- SCAddr0W and SCAddr0X
SCAddr0Y and SCAddr0Z
SCWrW* and SCWrX*
SCWrY* and SCWrZ*
TClock(0) and TClock(1)
RClock(0) and RClock(1)
- All input pads data are first latched into a processor clock-based register in the pad cell before they are captured into the Boundary-scan register in the Capture-DR (Boundary-scan) state. When the phase-locked loop is disabled, the processor clock is half the frequency of MasterClock. Therefore, when the TAP controller is in the Capture-DR (Boundary-scan) state, the data setup required at the input pads is more than two MasterClock periods before the rising edge of the JTCK.
- The output enable controls generated from the three most-significant bits of the Boundary-scan register are latched into a Processor Clock-based register before they actually enable the data onto the pads. Therefore, the delay from the rising edge of JTCK in the Update-DR (Boundary-scan) state to data valid at the output pins of the chip is greater than two MasterClock periods.
Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96
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