-Test Access Port (TAP)

14.3 JTAG Controller and Registers

Test Access Port (TAP)

The Test Access Port (TAP) consists of the four signal pins: JTDI, JTDO, JTMS, and JTCK. Serial test data and instructions are communicated over these four signal pins, along with control of the test to be executed.

As Figure 14-6 shows, data is serially scanned into one of the three registers (Instruction register, Bypass register, or the Boundary-scan register) from the JTDI pin, or it is scanned from one of these three registers onto the JTDO pin.

The JTDI input feeds the least-significant bit (LSB) of the selected register, whereas the most-significant bit (MSB) of the selected register appears on the JTDO output.

The JTMS input controls the state transitions of the main TAP controller state machine.

The JTCK input is a dedicated test clock that allows serial JTAG data to be shifted synchronously, independent of any chip-specific or system clocks.

Figure 14-6 JTAG Test Access Port

Data on the JTDI and JTMS pins is sampled on the rising edge of the JTCK input clock signal. Data on the JTDO pin changes on the falling edge of the JTCK clock signal.

TAP Controller

The processor implements the 16-state TAP controller as defined in the IEEE JTAG specification.

Controller Reset

The TAP controller state machine can be put into Reset state by one of the following:

deassertion of the VCCOk input resets the TAP controller
keeping the JTMS input signal asserted through five consecutive rising edges of JTCK input sends the TAP controller state machine into its Reset state.

In either case, keeping JTMS asserted maintains the Reset state.

Controller States

The TAP controller has four states: Reset, Capture, Shift, and Update. They can reflect either instructions (as in the Shift-IR state) or data (as in the Capture-DR state).

When the TAP controller is in the Reset state, the value 0x7 is loaded into the parallel output latch, selecting the Bypass register as default. The three most significant bits of the Boundary-scan register are cleared to 0, disabling the outputs.
When the TAP controller is in the Capture-IR state, the value 0x4 is loaded into the shift register stage.
When the TAP controller is in the Capture-DR (Boundary-scan) state, the data currently on the processor input and I/O pins is latched into the Boundary-scan register. In this state, the Boundary-scan register bits corresponding to output pins are arbitrary and cannot be checked during the scan out process.
When the TAP controller is in the Shift-IR state, data is loaded serially into the shift register stage of the Instruction register from the JTDI input pin, and the MSB of the Instruction register's shift register stage is shifted onto the JTDO pin.
When the TAP controller is in the Shift-DR (Boundary-scan) state, data is serially shifted into the Boundary-scan register from the JTDI pin, and the contents of the Boundary-scan register are serially shifted onto the JTDO pin.
When the TAP controller is in the Update-IR state, the current data in the shift register stage is loaded into the parallel output latch.
When the TAP controller is in the Update-DR (Boundary-scan) state, data in the Boundary-scan register is latched into the register parallel output latch. Bits corresponding to output pins, and those I/O pins whose outputs are enabled (by the three MSBs of the Boundary-scan register), are loaded onto the processor pins.

Table 14-2 shows the boundary scan order of the processor signals.

Table 14-2 JTAG Scan Order of R4000 Processor Pins

Table 14-2 (cont.) JTAG Scan Order of R4000 Processor Pins

See the section titled Boundary-Scan Register earlier in this chapter, for a description of the last three output enable bits, 319:317.

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