14.3 JTAG Controller and Registers
Instruction Register
The JTAG Instruction register includes three shift register-based cells; this register is used to select the test to be performed and/or the test data register to be accessed. As listed in Table 14-1, this encoding selects either the Boundary-scan register or the Bypass register.
Table 14-1 JTAG Instruction Register Bit Encoding
The Instruction register has two stages:
- shift register
- parallel output latch
Figure 14-3 shows the format of the Instruction register.
Figure 14-3 Instruction Register
Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96
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