-Write Cycles

13.6 Operation of the Secondary Cache Interface

Write Cycles

There are two basic write cycles: a 4-word write cycle and an 8-word write cycle. The secondary cache write cycle begins with the assertion of an address onto the address pins.

This section describes both 4-word and 8-word write cycles, including timing diagrams.

4-Word Write Cycle

A 4-word write cycle has three timing parameters:

tWr1Dly delay from the assertion of the address to the assertion of SCWR*

tWrSUp delay from assertion of the second data double-word to the deassertion of SCWR*

tWrRc delay from the deassertion of SCWR* to the beginning of the next cycle

The timing parameter tWrRc is 0 for most cache designs. Note that the upper data doubleword and the lower data doubleword are normally driven one cycle apart; this reduces the peak current consumption in the output drivers.

Figure 13-4 illustrates the 4-word write cycle. Either the upper or lower data doubleword can be driven first.

Figure 13-4 Timing Diagram of a 4-Word Write Cycle

8-Word Write Cycle

An 8-word write cycle has one additional parameter beyond those used by the 4-word write cycle: tWr2Dly. This is the time period that begins when the low-order address bit SCAddr(0) changes and ends when SCWR* is asserted for the second time. The lower half of SCData is driven on the same edge as the change in SCAddr(0).

Figure 13-5 illustrates the 8-word write cycle.

Figure 13-5 Timing Diagram of an 8-Word Write Cycle

Notes on a Secondary Cache Write Cycle

When receiving data from the System interface, the first data doubleword can arrive several cycles before the second data doubleword. In this case, the cache state machine enters a wait-state that extends SCWR* until tWrSUp period after the second data item is transmitted.

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