13.6 Operation of the Secondary Cache Interface

Read Cycles

There are two basic read cycles: 4-word read and 8-word read.

Each secondary cache read cycle begins by driving an address out on the address pins. The output enable signal SCOE* is asserted at the same time.

This section describes both 4-word and 8-word read cycles, including timing diagrams.

4-Word Read Cycle

The 4-word read cycle has two user-accessible timing parameters:

tRd1Cyc read sequence cycle time, which specifies the time from the assertion of the SCAddr bus to the sampling of the SCData bus

tDis cache output disable time, which specifies the time from the end of a read cycle to the start of the next write cycle

Figure 13-2 illustrates the 4-word read cycle, including the two user-accessible timing parameters.



Figure 13-2 Timing Diagram of a 4-Word Read Cycle

8-Word Read Cycle

The 8-word read cycle has an additional user-accessible parameter beyond that of the 4-word read cycle described above: tRd2Cyc, the time from the first sample point to the second sample point.

In an 8-word read cycle, the low-order address bit, SCAddr(0), changes at the same time as the first read sample point.

Figure 13-3 illustrates the 8-word read cycle, including the three user-accessible timing parameters.



Figure 13-3 Timing Diagram of an 8-Word Read Cycle

Notes on a Secondary Cache Read Cycle

All read cycles can be aborted by changing the address; a new cycle begins with the edge on which the address is changed. Additionally, the period tDis after a read cycle can be interrupted any time by the start of a new read cycle. If a read cycle is aborted by a write cycle, SCOE* must be deasserted for the tDis period before the write cycle can begin.

Read cycles can also be extended indefinitely. There is no requirement to change the address at the end of a read cycle.

Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96

Generated with CERN WebMaker
statistics