13. Secondary Cache Interface

13.6 Operation of the Secondary Cache Interface

The secondary cache can be configured for various clock rates and static RAM speeds. All configurable parameters are specified in multiples of PClock, which runs at twice the frequency of the external system clock, MasterClock.

During boot time, secondary cache timing parameters are programmed through the boot-time mode bits, as described in Chapter 9. Table 13-1 lists the secondary cache timing parameters. The following sections describe secondary cache read and write cycles.

Table 13-1 Secondary Cache Timing Parameters

Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96

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