13. Secondary Cache Interface

13.3 Accessing a Split Secondary Cache

When the secondary cache is split into separate instruction and data portions, assertion of the high-order SCAddr bit, SCAddr(17), enables the instruction half of the cache.

It is possible to design a cache that supports both joint and split instruction/data configurations of less than the maximum cache size; in doing so, SCAddr(12:0) must address the cache in all configurations. SCAddr(17) must support the split instruction/data configuration, and any of SCAddr(16:14) bits can be omitted, because of the fixed width of the physical tag array.

Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96

Generated with CERN WebMaker
statistics