13.2 -Duplicating Signals

13. Secondary Cache Interface

13.2 Duplicating Signals

The buffered control signals control the speed of the Secondary Cache interface. Critical control signals are duplicated by design to minimize this limitation: the SCWR* signal and SCAddr(0) have four versions so that external buffers are not needed to drive them. When an 8-word
(256-bit) primary cache line is used, these signals can be controlled quickly, reducing the time of back-to-back transfers.

Each duplicated control signal can drive up to 11 SRAMs; therefore, a total of 44 SRAM packages can be used in the cache array. This allows a cache design using 16-Kbyte-by-64-bit, 64-Kbyte-by-4-bit, or 256-Kbyte-by-4-bit standard SRAM.*1

The benefit of duplicating SCAddr(0) is greater in systems that use fast sequential static cache RAM and an 8-word primary cache line. If SCAddr(0) is attached to the SRAM address bit that affects column decode only, the read cycle time should approximate the output enable time of the RAM. For fast static RAM, this cycle time should be half of the nominal read cycle time.

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