13. Secondary Cache Interface
13.1 Data Transfer Rates
The interface to the secondary cache maximizes service of primary cache misses. The Secondary Cache interface, SCData(127:0), supports a data rate that is close to the processor-to-primary-cache bandwidth during normal operation. To ensure that this bandwidth is maintained, each data, tag, and check pin must be connected to a single SRAM device.
The SCAddr bus, together with the SCOE*, SCDCS*, and SCTCS* signals, drives a large number of SRAM devices; because of this, one level of external buffering between the processor and the cache array is used.
Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96
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