cache. This interface consists of:
- a 128-bit data bus
- a 25-bit tag bus
- an 18-bit address bus
- various static random access memory (SRAM) control signals.
The 128-bit-wide data bus minimizes the primary cache miss penalty, and allows the use of standard low-cost SRAMs in the design of the secondary cache.
The remainder of the System interface signals are described in Chapter 8.
Chapter Contents
- 13.1 - Data Transfer Rates
-
- 13.2 - Duplicating Signals
-
- 13.3 - Accessing a Split Secondary Cache
-
- 13.4 - SCDChk Bus
-
- 13.5 - SCTAG Bus
-
- 13.6 - Operation of the Secondary Cache Interface
-
