12.10 System Interface Addresses
Sequential and Subblock Ordering
The order in which data is returned in response to a processor block read request can be programmed to sequential ordering or subblock ordering, using the boot-time mode control interface. Appendix C has more information about subblock ordering. Either sequential or subblock ordering may be enabled, as follows:
- If sequential ordering is enabled on a block read request, the processor delivers the address of the doubleword at the start of the block. An external agent must return the block of data sequentially from the beginning of the block.
- If subblock ordering is enabled, the processor delivers the address of the requested doubleword within the block. An external agent must return the block of data using subblock ordering, starting with the addressed doubleword.
NOTE: Only R4000SC and R4000MC configurations (using a secondary cache) can be programmed to use sequential ordering.
For block write requests, the processor always delivers the address of the doubleword at the beginning of the block; the processor delivers data beginning with the doubleword at the beginning of the block and progresses sequentially through the doublewords that form the block.
During data cycles, the valid byte lines depend upon the position of the data with respect to the aligned doubleword (this may be a byte, halfword, tribyte, quadbyte/word, quintibyte, sextibyte, septibyte, or an octalbyte/doubleword). For example, in little-endian mode, on a byte request where the address modulo 8 is 0, SysAD(7:0) are valid during the data cycles.
Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96
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