1.6 R4000 Processor

Data Formats and Addressing

When the R4000 processor is configured as a big-endian system, byte 0 is the most-significant (leftmost) byte, thereby providing compatibility with MC 68000, and IBM 370, conventions. Figure 1-4 shows this configuration.

Figure 1-4 Big-Endian Byte Ordering

When configured as a little-endian system, byte 0 is always the least-significant (rightmost) byte, which is compatible with iAPX, x86 and DEC VAX, conventions. Figure 1-5 shows this configuration.

Figure 1-5 Little-Endian Byte Ordering

In this text, bit 0 is always the least-significant (rightmost) bit; thus, bit designations are always little-endian (although no instructions explicitly designate bit positions within words).

Figures 1-6 and 1-7 show little-endian and big-endian byte ordering in doublewords.

Figure 1-6 Little-Endian Data in a Doubleword

Figure 1-7 Big-Endian Data in a Doubleword

The CPU uses byte addressing for halfword, word, and doubleword accesses with the following alignment constraints:

• Halfword accesses must be aligned on an even byte boundary (0, 2, 4...).
• Word accesses must be aligned on a byte boundary divisible by four (0, 4, 8...).
• Doubleword accesses must be aligned on a byte boundary divisible by eight (0, 8, 16...).

These instructions are used in pairs to provide addressing of misaligned words. Addressing misaligned data incurs one additional instruction cycle over that required for addressing aligned data.

Figures 1-8 and 1-9 show the access of a misaligned word that has byte address 3.

Figure 1-8 Big-Endian Misaligned Word Addressing

Figure 1-9 Little-Endian Misaligned Word Addressing

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