12.8 System Interface Cycle Time

Release Latency


Release latency
is generally defined as the number of cycles the processor can wait to release the System interface to slave state for an external request. When no processor requests are in progress, internal activity--such as refilling the primary cache from the secondary cache--can cause the processor to wait some number of cycles before releasing the System interface. Release latency is therefore more specifically defined as the number of cycles that occur between the assertion of ExtRqst* and the assertion of Release*.

There are three categories of release latency:

Table 12-9 summarizes the minimum and maximum release latencies for requests that fall into categories 1, 2, 3a and 3b. Note that the maximum and minimum cycle count values are subject to change.

Table 12-9 Release Latency for External Requests



Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96

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