-Secondary Cache Write Cycle Time

12.7 Data Rate Control

Secondary Cache Write Cycle Time

Behavior of the processor is undefined if, based on the secondary cache write cycle time, data is delivered to the processor faster than the processor can handle it. Secondary cache write cycle time is defined as the sum of the parameters:

TWr1Dly, TWrSUp, and TWrRc

These parameters are defined in Chapter 9, Table 9-1.

The rate at which the processor transmits data to an external agent is programmable at boot time through the boot-time mode control interface. The transmit data rate can be programmed to any of the data rates and data patterns listed in Table 12-6, as long as the programmed data rate does not exceed the maximum rate the processor can handle, based on the secondary cache write cycle time. The behavior of the processor is undefined if a programmed transmit data rate exceeds the maximum the processor can support.

Figure 12-41 shows a processor write request in which the processor transmit data rate is programmed as one doubleword every two cycles, using the data pattern DDxx.

Figure 12-41 Processor Write Request, Transmit Data Rate Reduced

Table 12-7 shows the maximum transmit data rates for a given set of secondary cache parameters, based on a PClock-to-SClock divisor of 2. To find the maximum allowable secondary cache write cycle time and secondary cache access time, multiply the maximum secondary cache numbers for each pattern by:

(PClock_to_SClock_Divisor)/2

The minimum number for these parameters is always the minimum access time supported by processor.

Table 12-7 Maximum Transmit Data Rates

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