12.7 Data Rate Control
Secondary Cache Transfers
The processor operates most efficiently if data is delivered in pairs of doublewords, since the secondary cache is organized as a 128-bit RAM array. The most efficient way of reducing the data rate is to deliver a pair of doublewords followed by some number of unused cycles, followed by another pair of doublewords. The secondary cache write cycle time should determine the rate at which this pattern is repeated. However, the processor accepts data in any pattern as long as the time between the transfer of any pair of odd-numbered doublewords is greater than, or equal to, the write cycle time of the secondary cache. Doublewords in the transfer pattern are numbered beginning at 0: the odd-numbered doublewords are the second, fourth, sixth, and so on.
Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96
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