1.6 R4000 Processor

CPU Instruction Set Overview

Figure 1-3 CPU Instruction Formats

Each format contains a number of different instructions, which are described further in this chapter. Fields of the instruction formats are described in Chapter 2.

Instruction decoding is greatly simplified by limiting the number of formats to these three. This limitation means that the more complicated (and less frequently used) operations and addressing modes can be synthesized by the compiler, using sequences of these same simple instructions.

The instruction set can be further divided into the following groupings:

• Load and Store instructions move data between memory and general registers. They are all immediate (I-type) instructions, since the only addressing mode supported is base register plus 16-bit, signed immediate offset.
• Computational instructions perform arithmetic, logical, shift, multiply, and divide operations on values in registers. They include register (R-type, in which both the operands and the result are stored in registers) and immediate (I-type, in which one operand is a 16-bit immediate value) formats.
• Jump and Branch instructions change the control flow of a program. Jumps are always made to a paged, absolute address formed by combining a 26-bit target address with the high-order bits of the Program Counter (J-type format) or register address (R-type format). Branches have 16-bit offsets relative to the program counter (I-type). Jump And Link instructions save their return address in register 31.
• Coprocessor instructions perform operations in the coprocessors. Coprocessor load and store instructions are
  I-type.
• Coprocessor 0 (system coprocessor) instructions perform operations on CP0 registers to control the memory management and exception handling facilities of the processor. These are listed in Table 1-18.
• Special instructions perform system calls and breakpoint operations. These instructions are always R-type.
• Exception instructions cause a branch to the general exception-handling vector based upon the result of a comparison. These instructions occur in both R-type (both the operands and the result are registers) and I-type (one operand is a 16-bit immediate value) formats.

Tables 1-2 through 1-17 list CPU instructions common to MIPS R-Series processors, along with those instructions that are extensions to the instruction set architecture. The extensions result in code space reductions, multiprocessor support, and improved performance in operating system kernel code sequences--for instance, in situations where run-time bounds-checking is frequently performed. Table 1-18 lists CP0 instructions.

Table 1-2 CPU Instruction Set: Load and Store Instructions

Table 1-3 CPU Instruction Set: Arithmetic Instructions (ALU Immediate)

Table 1-4 CPU Instruction Set: Arithmetic (3-Operand, R-Type)

Table 1-5 CPU Instruction Set: Multiply and Divide Instructions

Table 1-6 CPU Instruction Set: Jump and Branch Instructions

Table 1-7 CPU Instruction Set: Shift Instructions

Table 1-8 CPU Instruction Set: Coprocessor Instructions

Table 1-9 CPU Instruction Set: Special Instructions

Table 1-10 Extensions to the ISA: Load and Store Instructions

Table 1-11 Extensions to the ISA: Arithmetic Instructions (ALU Immediate)

Table 1-12 Extensions to the ISA: Multiply and Divide Instructions

Table 1-13 Extensions to the ISA: Branch Instructions

Table 1-14 Extensions to the ISA: Arithmetic Instructions (3-operand, R-type)

Table 1-15 Extensions to the ISA: Shift Instructions

Table 1-16 Extensions to the ISA: Exception Instructions

Table 1-17 Extensions to the ISA: Coprocessor Instructions

Table 1-18 CP0 Instructions

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