12. System Interface

12.7 Data Rate Control


The System interface supports a maximum data rate of one doubleword per cycle. The data rate the processor can support is directly related to the secondary cache access time; if the access time is too long, the processor cannot transmit and accept data at the maximum rate.

The rate at which data is delivered to the processor can be determined by the external agent--for example, the external agent can drive data and assert ValidIn* every n cycles, instead of every cycle. An external agent can deliver data at any rate it chooses, but must not deliver data to the processor any faster than the processor is capable of receiving it.

The processor only accepts cycles as valid when ValidIn* is asserted and the SysCmd bus contains a data identifier; thereafter, the processor continues to accept data until it receives the data word tagged as the last one.



Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96

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