12. System Interface
12.6 Processor and External Request Protocols
The following sections contain a cycle-by-cycle description of the bus arbitration protocols for each type of processor and external request. Table 12-5 lists the abbreviations and definitions for each of the buses that are used in the timing diagrams that follow.
Table 12-5 System Interface Requests
Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96
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