There is, however, one situation in which the execution of a Load Linked Store Conditional instruction sequence is visible, as indicated by the link address retained bit during a processor read request, as programmed by the SysCmd(2) bit. This situation occurs when the data location targeted by a Load Linked Store Conditional instruction sequence maps to the same cache line to which the instruction area containing the Load Linked Store Conditional code sequence is mapped. In this case, immediately after executing the Load Linked instruction, the cache line that contains the link location is replaced by the instruction line containing the code. The link address is kept in a register separate from the cache, and remains active as long as the link bit, set by the Load Linked instruction, is set.

The link bit, which is set by the load linked instruction, is cleared by a change of cache state for the line containing the link address, or by a Return From Exception.

In order for the Load Linked Store Conditional instruction sequence to work correctly, all coherency traffic targeting the link address must be visible to the processor, and the cache line containing the link location must remain in a shared state in every cache in the system. This guarantees that a Store Conditional executed by some other processor is visible to the processor as a coherence request, changing the state of the cache line containing the link location.

To accomplish this, a read request issued by the processor, causing the cache line containing the link location to be replaced. In the mean time, the link address retained bit is set, indicating the link address is being retained. This informs the external agent that, although the processor has replaced this cache line, the processor must still see any coherence traffic that targets this cache line.

Any snoop or intervention request that targets a cache line which is not present in the cache--but for which the snoop or intervention address matches the current link address while the link bit is set--returns an indication that the cache line is present in the cache in a shared state. This is consistent with the coherency model, since the processor never returns data, in response to an intervention request, for a cache line that is in the shared state. The shared response guarantees that the cache line containing the link location remains in a shared state in all other processor's caches, and therefore that any other processor attempting a store conditional to this link location must issue a coherence request in order to complete the store conditional.