
12.5 Handling Requests

External requests have a higher priority than uncached stores. When using the uncached store buffer on an R4400 processor, it is possible for the external agent to receive cached and uncached stores out of program order, as the example below illustrates. Figure 12-14 shows a cached and uncached store instruction sequence:
Figure 12-14 R4400 Processor Cached and Uncached Store Sequence
Referring to Figure 12-14, suppose an external intervention or snoop is issued to the R4400 processor while the uncached store is still in the store buffer (the uncached store data has not yet been stored off-chip). The cached store from Figure 12-14 has hit in the primary cache and is in the tag check (TC) stage of the pipeline (see Chapter 3 for a description of the pipeline stages). In this case, the external agent sees the state of the internal caches after the cached store but before the result of the uncached store is available off the chip. Figure 12-15 shows how a SYNC instruction can force the uncached store to occur before the cached store.
Figure 12-15 R4400 Processor Cached and Uncached Stores, Using SYNC





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