
12.5 Handling Requests

Secondary-Cache Mode
When the processor hits in the secondary cache, on a line that is marked either shared or dirty shared, the processor must issue an update or invalidate request and then wait to receive an acknowledge, before the store is complete. The processor checks the coherency attribute in the TLB for the page containing the cache line that is target of the store, to determine if the cache line is managed by either a write invalidate or write update cache coherency protocol.
No-Secondary-Cache Mode
In no-secondary-cache mode, all lines are set to the dirty exclusive state. This means store hits cause no bus transactions.





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