
12.5 Handling Requests

If the new cache line replaces a current dirty exclusive or dirty shared cache line, the current cache line must be written back before the new line can be loaded in the primary and secondary caches.
The processor examines the coherency attribute (cache coherency attributes are described in Chapter 11) in the TLB entry for the page that contains the requested cache line, and executes one of the following requests:
Table 12-3 Load Miss to Primary and Secondary Caches ![]()
If the current cache line needs to be written back and the coherency attribute for the requested cache line is sharable or update, the processor issues a cluster. The cluster consists of a coherent block read-with-write-forthcoming request for the cache line that contains the data element to be loaded, followed by a block write request for the current cache line.
If the current cache needs to be written back and the coherency attribute for the page containing the requested cache line is exclusive, the processor issues a cluster consisting of an exclusive read-with-write-forthcoming request, followed by a write request for the current cache line.
Table 12-3 lists these actions.
1. The processor issues a noncoherent read request*1 for the cache line that contains the data element to be loaded.
2. The processor then waits for an external agent to provide the read response.
If the current cache line must be written back, the processor issues a write request to save the dirty cache line in memory.
Generated with CERN WebMaker
Secondary-Cache Mode
In secondary-cache mode, if the current cache line does not have to be written back and the coherency attribute for the page that contains the requested cache line is not exclusive, the processor issues a coherent block read request for the cache line that contains the data element to be loaded. No-Secondary-Cache Mode
In no-secondary-cache mode, if the cache line must be written back on a load miss, the read request is issued and completed before the write request is handled. The processor takes the following steps:

Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96




![]()