-Interface Buses

12.2 System Interface Description

Interface Buses

Figure 12-1 shows the primary communication paths for the System interface: a 64-bit address and data bus, SysAD(63:0), and a 9-bit command bus, SysCmd(8:0). These SysAD and the SysCmd buses are bidirectional; that is, they are driven by the processor to issue a processor request, and by the external agent to issue an external request (see Processor and External Requests, in this chapter, for more information).

A request through the System interface consists of:

an address
a System interface command that specifies the precise nature of the request
a series of data elements if the request is for a write, read response, or update.

Figure 12-1 System Interface Buses

Address and Data Cycles

Cycles in which the SysAD bus contains a valid address are called address cycles. Cycles in which the SysAD bus contains valid data are called data cycles. Validity is determined by the state of the ValidIn* and ValidOut* signals (described in Interface Buses, in this chapter).

The SysCmd bus identifies the contents of the SysAD bus during any cycle in which it is valid. The most significant bit of the SysCmd bus is always used to indicate whether the current cycle is an address cycle or a data cycle.

During address cycles [SysCmd(8) = 0], the remainder of the SysCmd bus, SysCmd(7:0), contains a System interface command (the encoding of System interface commands is detailed in System Interface Commands and Data Identifiers, in this chapter).
During data cycles [SysCmd(8) = 1], the remainder of the SysCmd bus, SysCmd(7:0), contains a data identifier (the encoding of data identifiers is detailed in System Interface Commands and Data Identifiers, in this chapter).

Issue Cycles

There are two types of processor issue cycles:

processor read, invalidate, and update request issue cycles
processor write request issue cycles.

The processor samples the signal RdRdy* to determine the issue cycle for a processor read, invalidate, or update request; the processor samples the signal WrRdy* to determine the issue cycle of a processor write request.

As shown in Figure 12-2, RdRdy* must be asserted two cycles prior to the address cycle of the processor read/invalidate/update request to define the address cycle as the issue cycle.

Figure 12-2 State of RdRdy* Signal for Read, Invalidate, or Update Requests

As shown in Figure 12-3, WrRdy* must be asserted two cycles prior to the first address cycle of the processor write request to define the address cycle as the issue cycle.

Figure 12-3 State of WrRdy* Signal for Write Requests

The processor repeats the address cycle for the request until the conditions for a valid issue cycle are met. After the issue cycle, if the processor request requires data to be sent, the data transmission begins. There is only one issue cycle for any processor request.

The processor accepts external requests, even while attempting to issue a processor request, by releasing the System interface to slave state in response to an assertion of ExtRqst* by the external agent.

Note that the rules governing the issue cycle of a processor request are strictly applied to determine the action the processor takes. The processor either:

completes the issuance of the processor request in its entirety before the external request is accepted, or

releases the System interface to slave state without completing the issuance of the processor request.

In the latter case, the processor issues the processor request (provided the processor request is still necessary) after the external request is complete. The rules governing an issue cycle again apply to the processor request.

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