processor to access external resources needed to satisfy cache misses and uncached operations, while permitting an external agent access to some of the processor internal resources.
In the R4000MC configuration, the System interface also provides the processor with mechanisms to maintain the cache coherency of shared data, while providing an external agent the mechanisms to maintain system-wide multiprocessor cache coherency.
This chapter describes the System interface from the point of view of both the processor and the external agent.
Chapter Contents
- 12.1 - Terminology
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- 12.2 - System Interface Description
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- 12.3 - System Interface Protocols
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- 12.4 - Processor and External Requests
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- 12.5 - Handling Requests
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- 12.6 - Processor and External Request Protocols
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- 12.7 - Data Rate Control
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- 12.8 - System Interface Cycle Time
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- 12.9 - System Interface Commands and Data Identifiers
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- 12.10 - System Interface Addresses
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- 12.11 - Processor Internal Address Map
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