11.12 R4000 Processor Synchronization Support
LL and SC
MIPS instructions Load Linked (LL) and Store Conditional (SC) provide support for processor synchronization. These two instructions work very much like their simpler counterparts, load and store. The LL instruction, in addition to doing a simple load, has the side effect of setting a bit called the link bit. This link bit forms a breakable link between the LL instruction and the subsequent SC instruction. The SC performs a simple store if the link bit is set when the store executes. If the link bit is not set, then the store fails to execute. The success or failure of the SC is indicated in the target register of the store.
The link is broken in the following circumstances:*1
- if any external request (invalidate, snoop, or intervention) changes the state of the line containing the lock variable to invalid
- upon completion of an ERET (return from exception) instruction
- an external update to the cache line containing the lock variable
The most important features of LL and SC are:
- They provide a mechanism for generating all of the common synchronization primitives including test-and-set, counters, sequencers, etc., with no additional overhead.
- When they operate, bus traffic is generated only if the state of the cache line changes; lock words stay in the cache until some other processor takes ownership of that cache line.
Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96
Generated with CERN WebMaker
