1.6 R4000 Processor

Superpipeline Architecture

The R4000 processor exploits instruction parallelism by using an eight-stage superpipeline which places no restrictions on the instruction issued. Under normal circumstances, two instructions are issued each cycle.

The internal pipeline of the R4000 processor operates at twice the frequency of the master clock, as discussed in Chapter 3. The processor achieves high throughput by pipelining cache accesses, shortening register access times, implementing virtual-indexed primary caches, and allowing the latency of functional units to span more than one pipeline clock cycles.

Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96

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