-Sample Cycle: Coherent Read Request

11.11 Coherency Conflicts

Sample Cycle: Coherent Read Request

This section describes a multiprocessor system within which a coherent read request cycle*1 services a secondary cache load miss. The system has two processors, PA and PB, and two external agents linked to these processors, external agent A (EA) and external agent B (EB). The external agents connect the processors to a system bus. Each of the processors has its own secondary cache.

The sample cycle follows the steps below (these steps are also numbered in Figures 11-13, 11-14, and 11-15):

1. Processor B has a load miss within a sharable page.

2. Processor B issues a coherent read request (CRR) through EB.

3. The CRR is placed on the bus.

Figure 11-13 Cache Load Miss Cycle: Coherent Read Request

Figure 11-14 Cache Load Miss Cycle: External Intervention

4. As shown in Figure 11-14, external agent EA reads the CRR from the bus.

5. To service this CRR, EA issues an external intervention request (EIR) to processor A, PA.

6. PA receives the EIR and examines its secondary cache, SA.

7. Depending on the type of intervention request--based on the state of the SysCmd(3) bit--one of the following actions is taken:

If the cache line in SA is in the dirty exclusive state, the entire cache line is returned.
Otherwise, PA just returns the state of the secondary cache line.

In Figure 11-14 the retrieved data is in the dirty exclusive state (DE), servicing a load miss, when the state of cache line SA goes from dirty exclusive to dirty shared (DS),*2 indicating PA is owner of the line.

Figure 11-15 Cache Load Miss Cycle: Read Response

8. Figure 11-15 shows the cache state and cache data returned from PA, through EA to the bus.

9. This cache state and data are returned to EB.

10. EB issues a read response to PB.

11. PA remains owner of the cache line.

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