11.11 Coherency Conflicts
For pending processor coherent read requests, conflict detection could be added to a system similar to the one shown in Figure 11-12. In such a case, when the external agent sees a read response on the bus that conflicts with a pending processor coherent read request, the external agent does not issue an intervention request to the processor. Rather, it simply reacts as if an intervention request has been completed and the cache line is not present in the processor cache.
Similarly, when an external agent sees an invalidate request on the bus that conflicts with a pending processor coherent read request, it does not forward the invalidate request to the processor since the targeted cache line is absent from the processor cache. This scheme for conflict detection on processor coherent read requests could reduce the number of external intervention and invalidate requests issued to the processor. However, since the intervention and invalidate requests that would otherwise be issued to the processor cannot result in any state modification within the processor (since the targeted cache line is not present in the cache), conflict detection for processor coherent read requests is not necessary.
If the response to a coherent read request conflicts with a waiting processor write request, or with a processor write request that is transmitting data, the external agent detects the conflict and does not issue an intervention request to the processor. Instead, it reacts as if an intervention request has been completed and the line is in the dirty exclusive state. The external agent indicates takeover and supplies the read data to the read requester itself without disturbing the processor. After providing the read data to the read requester, the external agent must discard the write request if the read request was a read exclusive. In fact, the external agent can ignore the write request for either type of read, since processor-supplied read data is also written back to memory.
It is not possible for an invalidate request, or a write request that conflicts with a waiting processor write request, to appear on the system bus; before a processor write request can be issued, the state of the processor cache line must be set to dirty exclusive.
In the model system shown in Figure 11-12, an acknowledge for the invalidate is sent to the processor as soon as the invalidate is forwarded to the system bus. Therefore, while the external agent is waiting to become a bus master to forward the invalidate request, the external agent must detect, by using comparators, any external coherency request that conflicts with the unacknowledged invalidate. If a conflict is detected, the external agent must not forward the invalidate request to the system bus; instead, it must rescind the invalidate request and submit the conflicting external request to the processor, with a cancellation for the invalidate request.
If the response to a coherent read request conflicts with a waiting unacknowledged processor invalidate request, the external agent detects this conflict and does not forward the processor invalidate request to the bus. Instead, it discards the processor invalidate request and issues to the processor an intervention request that includes a cancellation. The processor then reevaluates its cache state and either reissues the invalidate request or issues a coherent read request.
If an invalidate request appears on the bus while the external agent has a processor invalidate request waiting, and the external agent detects the conflict, the external agent does not forward the processor invalidate request. Instead, it discards the processor invalidate request and issues an external invalidate request that includes a cancellation to the processor. The processor then reevaluates its cache state and either reissues the invalidate request or issues a coherent read request.
It is not possible for a write request that conflicts with a waiting processor invalidate request to appear on the system bus. To issue an invalidate request, the state of the cache line must be shared with every cache in the system that contains the line.
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Coherent Write Conflicts
As soon as a write request has been issued to the external agent, the external agent becomes responsible for the cache line. No conflicts are possible with a processor write request; however, the external agent must manage ownership of the cache line while it is waiting to acquire mastership of the system bus so that it can forward the write request. The external agent is responsible for the cache line from the time the issue cycle of the write request completes until the write request is forwarded to the system bus.Invalidate Conflicts
From the time the processor issues an invalidate request until that request is acknowledged, any external coherency request issued to the processor that conflicts with the unacknowledged invalidate must include a cancellation.
Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96
