-System Implications of Coherency Conflicts

11.11 Coherency Conflicts

System Implications of Coherency Conflicts

The constraints that the processor must place on the handling of coherency conflicts have certain implications on the design of a multiprocessor system using the R4000MC model. These constraints and their implications are described in this section.

System Model

To describe the implications of a coherency conflict, this section uses a system model that is snooping, split-read, and bus-based; I/O is not considered in this model.

The system model used in this example has the following components:

Four processor subsystems, each consisting of an R4000MC processor, a secondary cache, and an external agent (shown in Figure 11-12). The external agent communicates with the R4000MC processor, accepting processor requests and issuing external requests. Likewise, the system bus issues and receives bus requests.
A memory subsystem that communicates with main memory and the system bus.
A system bus that has the following characteristics:
- It is a multiple master, request-based, arbitrated bus. When an agent wishes to perform a transaction on the bus, it must request the bus and wait for global arbitration logic to assert a grant signal before assuming mastership of the bus. Once mastership has been granted, the agent can begin a transaction.
- It supports read transactions, read exclusive transactions, write transactions, and invalidate transactions.
- It is a split-read bus. This means bus operations can separate a read request from the return of its data.
- It is a snooping bus. All agents connected to the bus must monitor all bus traffic to correctly maintain cache coherency.
All of the TLB pages in the system have either a noncoherent or a sharable coherency attribute. (Noncoherent data is not allowed; noncoherent page attributes are used for instructions only.)
The sharable coherency attribute allows data to be shared between the four caches in the system by using a write invalidate cache coherency protocol.
The secondary cache states used are invalid, shared, clean exclusive, and dirty exclusive; the dirty shared secondary cache state is not allowed.

Figure 11-12 4-Processor System Illustrating Coherency Transactions

Given this system model, the following operations are described:

loads and stores

processor coherent read request and read response

processor invalidate

processor write

Load

A shown in Figure 11-12, when a processor misses in the primary and secondary caches on a load, the processor issues a read request. The subsystem external agent translates this to a read request on the bus. The returned data is loaded in either the clean exclusive or shared state, based on the shared indication returned with the read response data.*1

Store

In this system model, when a processor misses in the primary and secondary caches on a store, it issues a read request with exclusivity; this is translated to a read exclusive on the bus and data is loaded in the dirty exclusive state.

When a processor hits in the cache on a store to shared data, it issues an invalidate request that must be forwarded to the system bus. Before the store can be completed and the state changed to dirty exclusive, the invalidate request must be acknowledged.

Processor Coherent Read Request and Read Response

In this system model, when one of the external agents observes a coherent read request on the system bus, it does not take immediate action. Instead, the external agent issues an intervention request to its processor during the read response. This is referred to as a response complete read protocol; that is, the read is complete after the read response has occurred.

At the end of the read response, each of the external agents in the system model indicate whether it was able to obtain the state of the cache line that is the target of the intervention; if successful, the external agent indicates either sharing or takeover. Takeover occurs when an external agent discovers that its processor has a dirty exclusive copy of the cache line that is the target of the read.

The read response is extended until all external agents have obtained the state of the cache line from their processors.

In this system model, the response from an external agent at the end of a read response depends on whether the read request was an ordinary read request or a read exclusive request. These are described in the following sections.

Ordinary Read Request

For an ordinary read request, an external agent indicates shared at the end of the read response if it finds that its processor has a copy of the requested cache line in the clean exclusive or shared state.

An external agent indicates both shared and takeover at the end of a read response if it finds that its processor has a copy of the requested cache line in the dirty exclusive state. Having indicated takeover, the external agent supplies the contents of the cache line (returned by the processor in response to the intervention request) over the bus to the read requester, and causes the processor to change the state of the cache line to shared. At the same time the cache line is supplied to the read requester, it is also written back to memory.

Read Exclusive Request

For a read exclusive request, an external agent never indicates shared at the end of the read response, regardless of the state the cache line is in. Instead, the cache line must be in one of the following states:

If the current state of the cache line is clean exclusive or shared, the external agent changes the state of the cache line to invalid.
If the current state of the cache line is dirty exclusive, the external agent indicates takeover but not shared. Having indicated takeover, the external agent supplies the contents of the cache line to the read requester, and the processor changes the state of the cache line to invalid. While the cache line is supplied to the read requester, it is also written back to memory.

Processor Invalidate

In this system model, an invalidate request is considered complete as soon as it appears on the system bus. When an external agent observes an invalidate request on the system bus, it reacts as if the invalidate has changed the state of all caches at that instant.

Processor Write

In this system model, an external agent takes no action in response to a write request on the bus.

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