11.11 Coherency Conflicts
Conflicting external coherency requests cannot affect the behavior of the processor for pending processor coherent read requests. The processor only issues read requests for a range of physical addresses not currently in the cache; consequently, an external coherency request that targets the same physical address range will not find this physical address range in the cache. In such a case, the processor simply discards any external coherency requests that conflict with a pending processor coherent read request.
Cancellation is accomplished by setting the cancellation bit in the command for the coherency request [SysCmd(4)]. The processor, upon receiving an external coherency request with the cancellation bit set, considers its invalidate or update request to be acknowledged and cancelled. The processor again accesses the secondary cache to determine whether to reissue the invalidate or update request, or to issue a read request.
An external agent can only assert the cancellation bit during an unacknowledged processor invalidate or unacknowledged compulsory update request. If an external coherency request is issued with the cancellation bit set, and there is no unacknowledged processor invalidate or update request pending, the behavior of the processor is undefined.
If an external coherency request is issued with the cancellation bit set when a processor update request remains potential--in other words, while a processor read request is currently pending--the behavior of the processor is undefined.
Processor potential update requests cannot be cancelled. Potential updates are always issued with processor read requests and become compulsory only after the response to the processor read request is returned in one of the shared states.
It is not possible for external coherency requests to conflict with processor write requests, since the processor does not accept external requests while a processor write request is in progress.
Tables 11-7 and 11-8 summarize the interactions between processor coherency requests and conflicting external coherency requests, organized by processor state. These two tables show the processor in one of the following states:
Idle: no processor transactions are pending.
Read Pending: a processor coherent read request has been issued, but the read response has not been received.
Potential Update Unacknowledged: a processor update request has been issued while a processor coherent read request is pending but not yet acknowledged. By definition, therefore, the response to the coherent read request has not been received.
Invalidate or Update Unacknowledged: a processor invalidate or update request has been issued but has not yet been acknowledged. By definition, no coherent read request is pending.
Table 11-7 Summary of Coherency Conflicts: Invalidate and Update
Table 11-8 Summary of Coherency Conflicts: Intervention and Snoop
Generated with CERN WebMaker
Processor Coherent Read Requests
When the processor wants to service either a store or load cache miss for a page that has a coherent page attribute in the TLB (meaning the data passed back and forth should follow a defined multiprocessor coherency scheme), a coherent read request is used.Processor Invalidate or Update Requests
For processor invalidate or compulsory update requests, a cancellation mechanism indicates a conflict. For example, if an external coherency request is submitted while a processor invalidate or compulsory update request has been issued but not yet acknowledged, the conflict is resolved when the external agent cancels the processor invalidate or compulsory update.External Coherency Requests
If an external agent issues an external coherency request that conflicts with an unacknowledged processor invalidate or update request, without setting the cancellation bit, the system will operate in an undefined manner. In this case, the processor has no indication of the conflict and does not reevaluate the cache state to determine the correct action; it simply waits for an acknowledge to its invalidate or update request as it would for any invalidate or update request.
Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96
