11. Cache Organization, Operation, and Coherency
11.11 Coherency Conflicts
The R4000MC processor must handle competing coherency conflicts that arise from the processor and an external source. This section describes how coherency conflicts arise and how they are handled. A system model illustrates the implications of coherency conflicts in a multiprocessor environment; a coherent read request cycle is described at the end of this section.
Figure 11-11 shows the R4000MC processor issuing processor coherency requests and accepting external coherency requests.
Figure 11-11 Coherency Requests: Processor and External
The R4000MC processor issues the following processor coherency requests:
- processor coherent read requests
- processor invalidate requests
- processor update requests
The R4000MC processor accepts the following external coherency requests:
- external invalidate requests
- external update requests
- external snoop requests
- external intervention requests
Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96
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