-Strong Ordering

11.8 Cache Coherency Overview

Strong Ordering

Cache-coherent multiprocessor systems must obey ordering constraints on stores to shared data. A multiprocessor system that exhibits the same behavior as a uniprocessor system in a multiprogramming environment is said to be strongly ordered.

An Example of Strong Ordering

Given that locations X and Y have no particular relationship--that is, they are not in the same cache line--an example of strong ordering is as follows:

1. At time T, Processor A performs a store to location X and at the same time processor B performs a store to location Y.

2. At time T+1, Processor A does a load from location Y and at the same time processor B does a load from location X.

For the system to be considered strongly ordered, either processor A must load the new value of Y, or processor B must load the new value of X, or both processors A and B must load the new values of Y and X, respectively, under all conditions.

If processors A and B load old values of Y and X, respectively, under any conditions, the system is not strongly ordered.

Testing for Strong Ordering

Table 11-5 shows the algorithm for testing strong ordering.

Table 11-5 Algorithm for Testing Strong Ordering

For this algorithm to succeed, stores must have a global ordering in time; that is, every processor in the system must agree that either the store to location X precedes the store to location Y, or vice versa. If this global ordering is enforced, the test algorithm for strong ordering succeeds.

Restarting the Processor

Strong ordering requires precise control of a processor restart. Specifically, after completion of a processor coherency request, the system must ensure the completion of any cache state changes before allowing a processor restart.

The following sections describe processor restarts in a strong-ordered system after a processor coherency request.

Restart after a Coherent Read Request

Unless a processor invalidate or update request is unacknowledged after a coherent read request, the processor restarts (if sequential ordering is enabled) after the last word in the block has been transmitted to the processor.

Any external requests that must be completed before the read request is finished must be issued to the processor before the read response is issued.

Restart after a Coherent Write Request

The processor restarts after the coherent write request is completed. That is, the processor restarts after the last doubleword of data associated with the write request has been transmitted to the external agent, unless a processor read request is pending,*1 or a processor invalidate or update request is unacknowledged.

Restart after an Invalidate or Update Request

Following an invalidate or update request, the processor restarts after the external agent asserts IvdAck* or IvdErr*, unless a processor read request is pending or the processor is processing an external request when either IvdAck* or IvdErr* is asserted.

If either IvdAck* or IvdErr* is asserted during or after the first cycle that the external agent asserts ExtRqst*, the processor accepts the external request and completes any cache state changes associated with the external request before restarting.

If either IvdAck* or IvdErr* is asserted before, but not asserted during or after the first cycle that the external agent asserts ExtRqst*, the processor restarts before beginning the external request.

External requests must be completed before a processor invalidate or update completes. They can be completed, provided the processor receives an asserted ExtRqst* by the external agent either before or during the same cycle IvdAck* or IvdErr* is asserted.

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