11.8 Cache Coherency Overview

Cache Coherency Attributes

Cache coherency attributes are necessary to ensure the consistency of data throughout the multitude of caches that can be present in the multiprocessor environment.

Bits in the translation look-aside buffer (TLB) control coherency on a per-page basis. Specifically, the TLB contains 3 bits per entry that provide five possible coherency attributes; they are listed below and described more fully in the following sections.

Only uncached or noncoherent attributes can be used by an R4000PC or an R4000SC processor.

Table 11-4 summarizes the behavior of the processor on load misses, store misses, and store hits to shared cache lines for each of the five coherency attributes listed above. The following sections describe in detail the five coherency attributes.

Table 11-4 Coherency Attributes and Processor Behavior

Uncached

Lines within an uncached page are never in a cache. When a page has the uncached coherency attribute, the processor issues a doubleword, partial-doubleword, word, or partial-word read or write request directly to main memory (bypassing the cache) for any load or store to a location within that page.

Noncoherent

Lines with a noncoherent attribute can reside in a cache; a load or store miss causes the processor to issue a noncoherent block read request to a location within the cached page.

Sharable

Lines with a sharable attribute must be in a multiprocessor environment (using the R4000MC), since shared lines can be in more than one cache at a time. When the coherency attribute is sharable, the processor operates as follows:

In most systems, coherent read requests require snoops or directory checks, and noncoherent read requests do not.*1 Cache lines within the page are managed with a write invalidate protocol; that is, the processor issues an invalidate request on a store hit to a shared cache line.

Update

Lines with an update coherency attribute must be in a multiprocessor environment and can reside in more than one cache at a time. When the coherency attribute is update, the processor issues a coherent block read request for a load or store miss to a location within the page. Cache lines within the page are managed with a write update protocol; that is, the processor issues an update request on a store hit to a shared cache line.

Exclusive

Lines with an exclusive coherency attribute must be in a multiprocessor environment. When the coherency attribute is exclusive, the processor issues a coherent block read request that requests exclusivity for a load or store miss to a location within the page.

Cache lines within the page are managed with a write invalidate protocol.

NOTE: Load Linked-Store Conditional instruction sequences must ensure that the link location is not in a page managed with the exclusive coherency attribute.

Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96

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