11.7 -Cache State Transition Diagrams

11. Cache Organization, Operation, and Coherency

11.7 Cache State Transition Diagrams

The following sections describe the cache state diagrams that illustrate the cache state transitions for both the primary and secondary caches. Figures 11-9 and 11-10 are state diagrams of the primary and secondary caches, respectively.

When an external agent supplies a cache line, the initial state of the cache line is specified by the external agent (see Chapter 12 for a definition of an external agent). Otherwise, the processor changes the state of the cache line during one of the following events:

A store to a clean exclusive cache line causes the state to be changed to dirty exclusive in both the primary and secondary caches.
A store to a shared cache line--that is a line marked shared in the primary cache and either shared or dirty shared in the secondary cache--causes the processor to issue either an invalidate request or an update request (depending on the coherency attribute in the TLB entry for the page containing the cache line). And update page attribute causes an update request to be issued; a sharable page attribute causes an invalidate request to be issued.
- Upon successful completion of an invalidate, the processor completes the store and changes the state of the cache line to dirty exclusive in both the primary and secondary caches.
- Upon successful completion of an update, the processor completes the store and changes the state of the cache line to shared in the primary cache and dirty shared in the secondary cache if dirty shared mode is enabled. Dirty shared mode is programmable through the boot-time mode control interface (see Chapter 9 for a description of boot mode bits). If dirty shared mode is not enabled, the state of the primary and secondary caches are left in a shared state, after successful completion of an update.
A store to a dirty exclusive line remains in a dirty exclusive state.

These state diagrams do not cover the initial state of the system since the initial state is system dependent.

Figure 11-9 Primary Data Cache State Diagram

If the system is in no-secondary-cache mode, the cache state provided by the system is ignored, and the primary data cache state is set to dirty exclusive.

Figure 11-10 Secondary Cache State Diagram

The state of a secondary cache line is provided by the external agent and is set as follows:

Case 1. If the cache line is not present in another cache, it should be loaded in the clean exclusive state.

Case 2. If the cache line is retained by another cache and the state of the line in that cache remains shared or dirty shared, the line should be loaded in the shared state.

Case 3. If the cache line is retained by another cache and the cache relinquishes ownership to the processor making the read request, the line should be returned in the dirty shared state.

Case 4. If the cache line is retained by another cache and ownership is relinquished to memory, the line should be loaded in the shared state.

Case 5. If the cache line is relinquished by another cache and ownership is transferred to the processor making the read request, the line should be loaded in the dirty exclusive or dirty shared state.

For case 1, if the refill occurs on a store miss, the processor changes the cache line state to dirty exclusive. For each of the remaining cases listed above, the R4000 processor passes the state received from the external agent to the secondary cache.

The invalid state is never used for a refill. Software, however, should initialize the secondary cache to the invalid state after the system is powered up.

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