11. Cache Organization, Operation, and Coherency
If a primary cache line is in either the dirty exclusive or shared state and that cache line has been modified (the W bit is set), the processor writes this cache line back to memory (or the secondary cache, if it is present) when the line is replaced, either in the course of satisfying a cache miss or during the execution of a Write-back or Write-back Invalidate CACHE instruction.
If a secondary cache line is in either the dirty exclusive or dirty shared state, the processor writes this cache line back to memory when the line is replaced, either in the course of satisfying a cache miss or during the execution of a Write-back CACHE instruction.
Many systems, in particular multiprocessor systems, or systems employing I/O devices that are capable of DMA, require the system to behave as if the caches are always consistent both with memory and with each other. Schemes for maintaining consistency between more than one cache, or between caches and memory, are defined by the system cache coherency protocols (see the section titled Cache Coherency Overview later in this chapter). In the R4000 system, when the content of a cache line is inconsistent with memory, it is classified as dirty and is written back to memory according to the rules of the cache write-back policy.
When the processor writes a cache line back to memory, it does not ordinarily retain a copy of the cache line, and the state of the cache line is changed to invalid. However, there is one exception. The processor retains a copy of the cache line if a cache line is written back by the Hit Write-back cache instruction. The processor changes the retained cache line state to either clean exclusive if the secondary cache state was dirty exclusive before the write, or shared if the secondary cache state was dirty shared before the write. The processor signals this line retention during a write by setting SysCmd(2) to a 1, as described in Chapter 12.
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