1. Introduction

1.6 R4000 Processor

• the 64-bit architecture of the R4000 processor
• the superpipeline design of the CPU instruction pipeline (described in detail in Chapter 3)
• an overview of the System interface (described in detail in Chapter 12)
• an overview of the CPU registers (detailed in Chapters 4 and 5) and CPU instruction set (detailed in Chapter 2 and Appendix A)
• data formats and byte ordering
• the System Control Coprocessor, CP0, and the floating-point unit, CP1
• caches and memory, including a description of primary and secondary caches, the memory management unit (MMU), the translation lookaside buffer (TLB), and the Secondary Cache interface (described in more detail in Chapters 4 and 11). The Secondary Cache interface is detailed in Chapter 13.

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