-Organization of the Secondary Cache

11.3 R4000 Cache Description

Organization of the Secondary Cache

Each secondary cache line has an associated 19bit tag that contains bits 35:17 of the physical address, a 3-bit primary cache index, VA(14:12), and a 3bit cache line state. These 25 bits are protected by a 7bit ECC code.

The secondary cache is accessible to the processor and to the system interface; by setting the appropriate boot-mode bits, it can be configured at chip reset as a joint cache, or as separate I- and D-caches.

Figure 11-6 shows the format of the R4000 processor secondary-cache line. The size of the secondary cache line is set in the SB field of the Config register.

Figure 11-6 R4000 Secondary Cache Line Format

The R4000 processor secondary cache has the following characteristics:

write-back

direct-mapped

indexed with a physical address

checked with a physical tag

organized with either a 4-word (16-byte), 8-word (32-byte),
16-word (64-byte), or 32-word (128-byte) cache line.

The secondary cache state (CS) bits indicate whether:

the cache line data and tag are valid
the data is potentially present in the caches of other processors (shared versus exclusive)
the processor is responsible for updating main memory (clean versus dirty).

The PIdx field provides the processor with an index to the virtual address of primary cache lines that may contain data from the secondary cache line.

The PIdx field also detects a cache alias. Cache aliasing occurs when the physical address tag matches during a data reference to the secondary cache, but the PIdx field does not match in the virtual address. This indicates that the cache reference was made from a different virtual address than the one that created the secondary-cache line, and the processor signals a Virtual Coherency exception.

Generated with CERN WebMaker