
R4400 Microprocessor User's Manual

11. Cache Organization, Operation, and Coherency
This chapter describes in detail the cache memory: its place in the R4000 memory organization, individual operations of the primary and secondary caches, cache interactions, and an example of a cache coherency request cycle. The chapter concludes with a description of R4000 processor synchronization in a multiprocessor environment.
This chapter uses the following terminology:
- The primary cache may also be referred to as the P-cache.
- The secondary cache may also be referred to as the S-cache.
- The primary data cache may also be referred to as the D-cache.
- The primary instruction cache may also be referred to as the I-cache.
These terms are used interchangeably throughout this book.
Chapter Contents
- 11.1 - Memory Organization
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- 11.2 - Overview of Cache Operations
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- 11.3 - R4000 Cache Description
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- 11.4 - Cache States
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- 11.5 - Cache Line Ownership
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- 11.6 - Cache Write Policy
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- 11.7 - Cache State Transition Diagrams
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- 11.8 - Cache Coherency Overview
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- 11.9 - Maintaining Coherency on Loads and Stores
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- 11.10 - Manipulation of the Cache by an External Agent
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- 11.11 - Coherency Conflicts
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- 11.12 - R4000 Processor Synchronization Support
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Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96




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