-Connecting to a Gate-Array Device

10.5 Connecting Clocks to a System without Phase Locking

Connecting to a Gate-Array Device

When connecting to a gate-array device, both RClock and TClock are used within the gate-array. The gate array internally buffers RClock and uses this buffered version to clock registers that sample processor outputs.

These sampling registers should be immediately followed by staging registers clocked by an internally buffered version of TClock. This buffered version of TClock should be the global system clock for the logic inside the gate array and the clock for all registers that drive processor inputs. Figure 10-6 is a block diagram of this circuit.

Staging registers place a constraint on the sum of the clock-to-Q delay of the sample registers and the setup time of the staging registers inside the gate arrays, as shown in the following equation:

Figure 10-6 is a block diagram of a system without phase lock, using the R4000 processor with an external agent implemented as a gate array.

Figure 10-6 Gate-Array System without Phase Lock, using the R4000 Processor

In a system without phase lock, the transmission time for a signal from the processor to an external agent composed of gate arrays can be calculated from the following equation:

Transmission Time = (75 percent of TClock period) - (tDO for R4000) + (Minimum External Clock Buffer Delay) - (External Sample Register Setup Time) - (Maximum Clock Jitter for R4000 Internal Clocks) - (Maximum Clock Jitter for RClock)

The transmission time for a signal from an external agent composed of gate arrays to the processor in a system without phase lock can be calculated from the following equation:

Transmission Time = (TClock period) - (tDS for R4000) - (Maximum External Clock Buffer Delay) - (Maximum External Output Register Clock-to-Q Delay) - (Maximum Clock Jitter for TClock) - (Maximum Clock Jitter for R4000 Internal Clocks)

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