10.3 System Timing Parameters
Phase-Locked Loop (PLL)
The processor aligns SyncOut, PClock, SClock, TClock, and RClock with internal phase-locked loop (PLL) circuits that generate aligned clocks based on SyncOut/SyncIn. By their nature, PLL circuits are only capable of generating aligned clocks for MasterClock frequencies within a limited range.
Clocks generated using PLL circuits contain some inherent inaccuracy, or jitter; a clock aligned with MasterClock by the PLL can lead or trail MasterClock by as much as the related maximum jitter allowed by the individual vendor.
Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96
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