10. Clock Interface
10.3 System Timing Parameters
As shown in Figures 10-3 and 10-4, data provided to the processor must be stable a minimum of tDS nanoseconds (ns) before the rising edge of SClock and be held valid for a minimum of tDH ns after the rising edge of SClock.
Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96
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