1. Introduction

1.3 Processor General Features

• Full 32-bit and 64-bit Operations. The R4000 processor contains 32 general purpose 64-bit registers. (When operating as a 32-bit processor, the general purpose registers are 32-bits wide.) All instructions are 32 bits wide.
• Efficient Pipeline. The superpipeline design of the processor results in an execution rate approaching one instruction per cycle. Pipeline stalls and exceptional events are handled precisely and efficiently.
• MMU. The R4000 processor uses an on-chip TLB that provides rapid virtual-to-physical address translation.
• Cache Control. The R4000 primary instruction and data caches reside on-chip, and can each hold 8 Kbytes. In the R4400 processor, the primary caches can each hold 16 Kbytes. Architecturally, each primary cache can be increased to hold up to 32 Kbytes. An off-chip secondary cache (R4000SC and R4000MC processors only) can hold from 128 Kbytes to 4 Mbytes. All processor cache control logic, including the secondary cache control logic, is on-chip.
• Floating-Point Unit. The FPU is located on-chip and implements the ANSI/IEEE standard 754-1985.

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