9.2 Reset Signal Description
Warm Reset
To execute a warm reset, the Reset* input is asserted synchronously with MasterClock. It is then held asserted for at least 64 MasterClock cycles before being deasserted synchronously with MasterClock. The processor internal clocks, PClock and SClock, and the System interface clocks, TClock and RClock, are not affected by a warm reset. The boot-time mode control serial data stream is not read by the processor on a warm reset. A warm reset forces the processor to start with a Soft Reset exception. For information about saving processor states, see the description of the Soft Reset exception in Chapter 5.
The master clock output, MasterOut, can be used to generate any reset-related signals for the processor that must be synchronous with MasterClock.*1
After a power-on reset, cold reset, or warm reset, all processor internal state machines are reset, and the processor begins execution at the reset vector. All processor internal states are preserved during a warm reset, although the precise state of the caches depends on whether or not a cache miss sequence has been interrupted by resetting the processor state machines.
Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96
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