9.2 Reset Signal Description

Cold Reset

A cold reset can begin anytime after the processor has read the initialization data stream, causing the processor to start with the Reset exception. For information about saving processor states, see the description of the Reset exception in Chapter 5.

A cold reset requires the same sequence as a power-on reset except that the power is presumed to be stable before the assertion of the reset inputs and the deassertion of VCCOk.

To begin the reset sequence, VCCOk must be deasserted for a minimum of at least 64 MasterClock cycles before reassertion.

Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96

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